1. Field of the Invention
This invention relates generally to battery backed-up semiconductor devices, and more particularly to a VSS switching scheme for battery backed-up semiconductor devices.
2. Background of the Invention
Battery backed-up semiconductor devices offer the advantage of providing uninterrupted power to the semiconductor device and are used in many types of applications, including 5 volt, 3.3 volt, and 3.0 volt applications. The semiconductor device is typically provided with power from a primary power supply, such as Vcc, so long as the primary power supply is adequate. When the primary power supply drops below an acceptable voltage level, however, the device switches from the primary power supply to the battery supply.
The configuration of the switching mechanism in a battery backed-up semiconductor device is determined by the semiconductor process used to manufacture the device. If the semiconductor manufacturing process uses an N-type substrate, the N-type substrate is connected to the positive supply voltage, normally Vcc. The switching of the voltage from the primary power supply to the battery for such an N-type substrate semiconductor device must occur in either the Vcc line located in the N-type substrate or the Vss located in the P-type wells of the device. It is common practice in the industry for battery backed-up semiconductors to accomplish this switching from the primary power supply to the back-up battery by placing a switch in the primary power supply, normally the Vcc supply, as demonstrated in FIG. 1.
Referring to FIG. 1, an N-type substrate, P-well, semiconductor device 10 using a typical Vcc switching configuration is shown. There are four parts of the semiconductor device that must be powered: the input/output circuitry 22 of the device, the guard rings 24 of the device, the internal circuitry 26 of the device, and critical internal circuitry 28 of the device. The input and output circuitry 22 is representative of any circuitry of the device, such as an input buffer and output driver, that is connected to a pad of the device. The guard rings 24 shown are just one implementation of guard rings that can be used to protect the circuitry internal to the device from internal bi-polar conditions to which the device is subjected. One of ordinary skill in the art will recognize that various types of guard ring configurations known in the industry may be used. Internal circuitry 26 is representative of internal circuitry of the device 10 that need not have power constantly supplied to it. Critical internal circuitry 28 refers to circuitry of the device 10 that must receive uninterrupted power in order to prevent data corruption of the device. Examples of critical internal circuitry 28 include array and/or clock and oscillator and support circuitry. For instance, as is well known in the art, a Zeropower.RTM. device will have an array and support circuitry only whereas a Timekeeper.RTM. device will have clock and oscillator and support circuitry and can be supplied with or without a memory array.
As shown in FIG. 1, there are potentially three voltages supplied to the semiconductor device: Vcc pad 16, Vcc-switched 18, and Vss pad 20. Vcc pad 16 is the primary power supply, such as 5 volts or 3.3 volts or 3.0 volts, depending on the type of system used, that is supplied to a pad of the device. Vcc-switched 18 is the battery backed-up power that is provided to the device when Vcc pad is no longer adequate to supply power to the device. Vss pad 20 is the nominal, or ground, voltage potential supplied to a pad of the device. The figure clearly shows that the Vcc pad and Vcc-switched voltages are both supplied to the N-substrate 12 of the device while the Vss pad is supplied to the P-wells 14 of the device. If the process were reversed to use a P-type substrate, the switching would occur in the Vcc line located in the N-type wells of the device.
Referring now to FIG. 2, a circuit representation 30 of the N-substrate, P-well Vcc switched device of FIG. 1 is shown. Control signals Vccok 34 and Vccok bar 36 control the switching of battery 32 in and out of the circuit 30. Sleep mode signal 38 is supplied to sleep mode latch 40 and is used to preserve the battery 32 of the device by selectively disabling the array 28a and clock & oscillator 28b so that the device may be shipped or stored. As in FIG. 1, input/output circuitry 22 is supplied with both the Vcc pad 16 and Vss pad 20 voltages. Array 28a and oscillator & clock 28b are examples of critical internal circuitry 28 and are supplied with Vss pad 20 and with either Vcc pad voltage 16 or Vcc-switched voltage 18 as controlled by Vccok signal 34 and Vccok bar signal 36; Vccok signal 34 and Vccok bar signal 36, as indicated by their signal names, reflect whether Vcc pad signal 16 is sufficient to supply voltage to the device. Thus, array 28a and oscillator & clock 28b are supplied with Vcc-switched voltage 18 only if Vcc pad voltage 16 becomes insufficient in magnitude as reflected in control signals Vccok 34 and Vccok bar 36.
There are problems associated with switching the substrate of the battery backed-up device between the primary power supply and the back-up battery as shown in FIGS. 1 and 2. An external event, such as an undershoot condition, while the device is being supplied by battery power, can short the potential across the high impedance battery path, thereby causing signals of the device to be shorted or coupled to the device substrate and corrupt data stored in the semiconductor device. When undershoot occurs on an input pad or an output pad of the device, a forward biased condition is formed from the well to the input or output pad which forms a bi-polar transistor shorting the input condition to the substrate. If the input event goes below ground, the substrate will follow with the normal emitter to drain voltage. Pulling Vcc down below ground creates paths internal to the device through which data stored by the device can be leaked.
It is therefore desirable to be able to provide switching between a primary power supply and a battery supply of a semiconductor device in a manner that prevents corruption of the device due to undershoots and other events that can cause corruption of data stored by the device.